1. Field of the Invention
The present invention relates to a method of manufacturing a nonvolatile semiconductor memory and more particularly to a method of manufacturing a floating-gate nonvolatile semiconductor memory having a reduced gate space.
2. Description of the Related Art
EEPROM is a nonvolatile read only semiconductor memory in which information can be electrically written or erased. Thus, EEPROM is widely used for a microcomputer. A memory cell employing EEPROM is, for example, disclosed in an article "Reviews and Prospects of Non-Volatile Semiconductor Memories", IEICE TRANSACTIONS VOL. E 74, NO. 4, April 1991, pp. 868-874.
In the EEPROM, it is prevailed to write or erase information by injecting or discharging electrons into or from a floating gate through a thin oxide film formed on a drain region of a memory transistor by the tunnel current of Fowler-Nordheim.
For the purpose of improving the integration density in such a floating-gate EEPROM, the reduction of both the length of each floating gate and the space between every two floating gates has been developed. For this purpose, in the photolithography process for forming the floating gate, the exposure is performed by a reduced projection aligner.
However, even when the exposure is performed by the reduced projection aligner, there is a limit in reduction of both the length of each floating gate and the space between every two floating gates due to the resolution of the reduced projection aligner. For example, in the case of the aligner employing an i ray with 365 nm wavelength, the minimum dimension is limited to 0.5 .mu.m. Therefore, there is also a limit in integration of EEPROM.
As for a method of manufacturing EEPROM wherein the space between the floating gates is reduced to less than the minimum dimension which is determined by the resolution of the reduced projection aligner, there is known a method disclosed in an article "A 2.3 .mu.m.sup.2 Memory Cell Structure For 16 Mb NAND EEPROMs", IEDM 90 pp. 103-106 for example. In this method, however, it is necessary to form etching masks such that each etching mask has a configuration corresponding to the gate configuration and the etching masks are disposed at positions where the gates are to be formed with a space between two adjacent etching masks near the limit of the resolution of the reduced projection aligner, and to form a photo resist film of narrow width within the space so as not to contact with the etching masks adjacent thereto. Therefore, it involves a problem that it is practically difficult to perform the positioning of the photo resist film.